Technical Field
The present disclosure relates generally to semiconductor devices, and more particularly to a structure and fabrication method for large scale integration and cooling of devices.
Description of the Related Art
With standard CMOS technology coming to its limits of performance enhancements, methods to improve system performance without substantial individual device performance improvements are increasingly needed. One such method is 3D integration, which allows for much higher bandwidth communication between system components integrated into a stack than would otherwise be possible. Such short range interconnects reduce interconnect drive power. However, stacking high power devices creates difficulty in removing the heat from the devices, as the thermal resistance associated with additional layers greatly increases the temperature of high power layers buried in the stack.
One solution to this problem is pushing coolant through the stack. However, the Through Silicon Vias (TSVs) developed for the most advanced silicon process nodes limit die thickness to 50 microns or so, limiting the realizable coolant channel size. With typical large processor dies, it is not possible to push adequate coolant through such channels at reasonable pressures.